The present disclosure relates to an internal voltage generating circuit employing a boost circuit.
In recent years, flash memories, which are non-volatile semiconductor memory devices, require data read operation and data write operation which are performed using a single power source voltage or a low power source voltage. To achieve this, a boost circuit for supplying a boosted voltage or a negative boosted voltage during each operation is required on a chip. Also, in CMOS processes, a voltage generated by a boost circuit is used as a power source to improve characteristics of an analog circuit.
FIG. 9 shows a configuration of an internal voltage generating circuit 900 which is disclosed in U.S. Pat. No. 5,999,475. The internal voltage generating circuit 900 includes a first boost circuit 901 which performs boost operation in synchronization with a clock signal CLK and a complementary clock signal XCLK to output a first boosted voltage VPUMP1 through a first output node N1, a second boost circuit 902 which similarly performs boost operation in synchronization with the clock signals CLK and XCLK to output a second boosted voltage VPUMP2 through a second output node N2, and a high voltage switch circuit 903 which causes a path between the first output node N1 and the second output node N2 to be in the conductive or non-conductive state.
The first boost circuit 901 includes a first high voltage detecting circuit 904 which, when a first control signal PPE1 is activated, detects a voltage level of the first boosted voltage VPUMP1 and sets a first sense signal CKE1 to be in the active or inactive state, a first CLK gate circuit 905 which outputs the clock signals CLK and XCLK as first boost clock signals PCK1 and XPCK1 in response to the first sense signal CKE1, and a first charge pump circuit 906 which performs boost operation in synchronization with the first boost clock signals PCK1 and XPCK1 to output the first boosted voltage VPUMP1 through the first output node N1.
The second boost circuit 902 includes a second high voltage detecting circuit 907 which, when a second control signal PPE2 is activated, detects a voltage level of the second boosted voltage VPUMP2 and sets a second sense signal CKE2 to be in the active or inactive state, a second CLK gate circuit 908 which outputs the clock signals CLK and XCLK as second boost clock signals PCK2 and XPCK2 in response to the second sense signal CKE2, and a second charge pump circuit 909 which performs boost operation in synchronization with the second boost clock signals PCK2 and XPCK2 to output the second boosted voltage VPUMP2 through the second output node N2.
The high voltage switch circuit 903 is controlled in accordance with a control signal XPPE1 complementary to the first control signal PPE1 and a sense signal XCKE1 complementary to the first sense signal CKE1. When the operation of the internal voltage generating circuit 900 is started, the high voltage switch circuit 903 causes a path between the first output node N1 and the second output node N2 to be in the conductive state. After a voltage level of the first output node N1 becomes at a predetermined voltage level, the high voltage switch circuit 903 causes the path between the first output node N1 and the second output node N2 to be in the non-conductive state.
FIG. 10 shows details of the first charge pump circuit 906. The first charge pump circuit 906 includes boost capacitances Ca1 to Ca4 which are boosted in synchronization with the first boost clock signals PCK1 and XPCK1, charge transfer transistors Ta1 to Ta4 which transfer boosted charge from the previous stage to the next stage, and a backflow preventing circuit Ta5 which prevents backflow of charge of the first output node N1 (four-stages-one-parallel arrangement).
FIG. 11 shows details of the second charge pump circuit 909. The second charge pump circuit 909 includes boost capacitances Cb1 to Cb6 which are boosted in synchronization with the second boost clock signals PCK2 and XPCK2, charge transfer transistors Tb1 to Tb6 which transfer boosted charge from the previous stage to the next stage, and a backflow preventing circuit Tb7 which prevents backflow of charge of the second output node N2 (six-stages-one-parallel arrangement).
Here, the first and second charge pump circuits 906 and 909 receive a power source voltage VDD through first and second input terminals NIN1 and NIN2 and generate the first and second boosted voltages VPUMP1 and VPUMP2, respectively. Output voltages and output currents of the first and second charge pump circuits 906 and 909 are assumed to have the following relationships. Specifically, it is assumed that the boosted voltage VPUMP1 of the first charge pump circuit 906 is lower than the boosted voltage VPUMP2 of the second charge pump circuit 909, and a current supply capability IPUMP1 of the first charge pump circuit 906 is larger than a current supply capability IPUMP2 of the second charge pump circuit 909. Moreover, for example, it is assumed that the boost capacitances Ca1 to Ca4 of the first charge pump circuit 906 each have a capacitance value of 5 pF, and the boost capacitances Cb1 to Cb6 of the second charge pump circuit 909 each have a capacitance value of 1 pF.
FIG. 12 shows operational waveforms in FIGS. 9 to 11. The boost operation will be briefly described with reference to FIG. 12.
(Time T0)
An initial state of the circuit is shown. Both the first control signal PPE1 and the second control signal PPE2 are at “L.”
(Time T1)
At time T1, the first control signal PPE1 transitions from “L” to “H.” In this case, the first boosted voltage VPUMP1 at the first output node N1 has not reached a first target voltage VPP1_TARGET, and therefore, the first high voltage detecting circuit 904 outputs “L” as the first sense signal CKE1. As a result, the first CLK gate circuit 905 outputs the clock signals CLK and XCLK as the first boost clock signals PCK1 and XPCK1, and the first charge pump circuit 906 starts the boost operation in synchronization with the first boost clock signals PCK1 and XPCK1.
Similarly, the second control signal PPE2 transitions from “L” to “H.” In this case, the second boosted voltage VPUMP2 at the second output node N2 also has not reached a second target voltage VPP2_TARGET, and therefore, the second high voltage detecting circuit 907 outputs “L” as the second sense signal CKE2. As a result, the second CLK gate circuit 908 outputs the clock signals CLK and XCLK as the second boost clock signals PCK2 and XPCK2, and the second charge pump circuit 909 starts the boost operation in synchronization with the second boost clock signals PCK2 and XPCK2.
Thus, since the first sense signal CKE1 is at “L,” the sense signal XCKE1 complementary to this is at “H,” and therefore, the high voltage switch circuit 903 is in the conductive state. As a result, charging of the first output node N1 and the second output node N2 is started by the first charge pump circuit 906 and the second charge pump circuit 909.
(Time T2)
At time T2, while the high voltage switch circuit 903 remains in the conductive state, the first output node N1 and the second output node N2 are charged at the same rate by the first charge pump circuit 906 and the second charge pump circuit 909.
(Time T3)
At time T3, when the first boosted voltage VPUMP1 has reached the first target voltage VPP1_TARGET, the first sense signal CKE1 of the first high voltage detecting circuit 904 transitions from “L” to “H,” and the first CLK gate circuit 905 fixes the first boost clock signal PCK1 to “L” and its complementary signal XPCK1 to “H.” As a result, the boost operation of the first charge pump circuit 906 is stopped, and at the same time, the high voltage switch circuit 903 transitions from the conductive state to the non-conductive state, so that the first output node N1 and the second output node N2 are disconnected.
During a “Phase1” period from time T1 to time T3 that the high voltage switch circuit 903 is in the conductive state, the second output node N2 of the second charge pump circuit 909 having the low current supply capability IPUMP2 is rapidly charged to the first target voltage VPP1_TARGET by the first charge pump circuit 906 having the high current supply capability IPUMP1. At time T3, the internal voltage generating circuit 900 transitions from the “Phase 1” period to a “Phase2” period during which the high voltage switch circuit 903 is in the non-conductive state, and the first charge pump circuit 906 and the second charge pump circuit 909 operate independently of each other. Thereafter, Phase 2 continues.
(Time T4)
At time T4, the second output node N2 is charged using only the second charge pump circuit 909 which has the boost capacitances Cb1 to Cb6 (=1 pF) which are ⅕ of the first boost capacitances Ca1 to Ca4 (=5 pF) of the first charge pump circuit 906. At time T5, the second output node N2 reaches the second target voltage VPP2_TARGET. During Phase2 that the second output node N2 is charged using only the second charge pump circuit 909 having the low current supply capability IPUMP2, a change in voltage per unit time at the second output node N2 is smaller than that during Phase1.
Thereafter, the logic of the first sense signal CKE1 is inverted, depending on the voltage level of the first output node N1, and the logic of the second sense signal CKE2 is inverted, depending on the voltage level of the second output node N2. Thus, the first charge pump circuit 906 and the second charge pump circuit 909 repeatedly perform intermittent operation to hold the respective voltage levels.
As described above, the first output node N1 of the first charge pump circuit 906 having the high current supply capability IPUMP1 and the second output node N2 of the second charge pump circuit 909 having the low current supply capability IPUMP2 are controlled into the conductive/non-conductive state by the high voltage switch circuit 903. As a result, a voltage setup time for the second output node N2 of the second charge pump circuit 909 having the low current supply capability IPUMP2 can be reduced while preventing an increase in area of the internal voltage generating circuit 900.